Semiconductor memory

ABSTRACT

There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

BACKGROUND OF THE INVENTION

1.Field of the Invention

The present invention relates to a technology of highly integratedsemiconductor memory and more specifically to a technology effectivelyapplied to the disposition of a redundant memory cell and to a layoutmethod of word drivers and sense amplifiers connected to the redundantmemory cell.

2. Description of the Related Art

In the field of highly integrated semiconductor memories examined by theinventor, a technology of having a small number of redundant memorycells in addition to normal memory cells and of switching an access tothe redundant memory cell when the normal memory cell is defective iswidely used in order to improve the production yield.

As for the semiconductor memory having the redundant memory cells inaddition to the normal memory cells as described above, there is atechnology described in Japanese Patent Publication No. 2555252 entitled“Semiconductor Memory Device” for example. According to this technology,column redundancy is implemented by having a normal memory cell arrayand a redundant memory cell array in which a plurality of normal memorycell array blocks and a plurality of redundant memory cell array blocksare controlled in common by respective column decoders.

Noticing on the high integration of the semiconductor memory having theredundant memory cells in addition to the normal memory cells asdescribed above, the inventor examined the disposition of the redundantmemory cell and the layout method of word drivers and sense amplifiersconnected to the redundant memory cell. The contents examined by theinventor will be explained below by using FIG. 10.

FIG. 10 shows the disposition of the redundant memory cell. Thisredundant memory cell is positioned at the peripheral part of a normalmemory cell array 15 as shown in FIG. 10(a). Further, sense amplifierregions 16, sub-word driver regions 17 and their intersection regions 18are disposed adjacent to and around the memory cell array 15 as shown inFIG. 10(b).

By the way, with the high integration of the semiconductor memory, whilethe plane size of the memory cell may be refined further by forming itin 3-D, direct peripheral circuits such as the word drivers and senseamplifiers connected with the memory cell must be reduced in the planedirection in correspondence to the memory cell. However, their layout isnot easy because they are different from the memory cell and cannot beformed in 3-D.

Then, as a countermeasure thereof, there has been widely used a methodof reducing an occupied area by sharing contacts, through holes, powersources and signal lines in a plurality of units of those circuits in arepeating pitch in which a plurality of memory cells are put together.For instance, it has been applied in the layout unit of word driverscorresponding to 16 word lines W and in the layout unit of senseamplifiers corresponding to 16 bit lines BL.

Meanwhile, along with the high integration of the memory, the yield ofthe redundant memory cell has also become a problem. Then, the redundantmemory cell is disposed at the center of an array where themanufacturing condition is stable to make it alive. Because its testbefore setting a fuse may be eliminated or may be simplified if theredundant memory cell is surely alive, the whole test time may beshortened.

However, it has been difficult to lay out only the sub-word drivers orsense amplifiers related to the redundant memory cell specially becausethe number of word lines or bit lines of the redundant memory cell issmaller than the layout units. It is because the layout unit is toosmall so that the contacts, through holes, power sources and signallines cannot be shared as described above. Further, there has been apossibility that the characteristics and yield of the sub-word driversor sense amplifiers for the redundant memory cell become abnormal if therepeated shapes are different.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the invention to provide a semiconductormemory which allows a redundant memory cell to be disposed at the centerwhile maintaining the continuity of layout units of direct peripheralcircuits and allows the total yield of the memory cell and the directperipheral circuits to be improved by an efficient layout method ofsub-word drivers and sense amplifiers for disposing the redundant memorycell at the center of a memory cell array.

The above-mentioned and other objects and the novel characteristics ofthe invention will be apparent from the following description and theaccompanying drawings.

The summary of the typical one of the inventions disclosed in thepresent specification will explained below briefly.

The inventive semiconductor memory is arranged such that even if aredundant memory cell is disposed at the center of a memory cell array,the same layout unit with the normal memory cell is used for the layoutof sub-word drivers and sense amplifiers and the sub-word drivers andsense amplifiers which are increased due to the redundant memory cell isadjusted by a related circuit of the normal memory cell at the end ofthe memory cell array while maintaining the same repetition. Further,the changing point of the redundant memory cell and the normal memorycell is realized by replacing a control signal of the sub-word driversand sense amplifiers.

This method allows the redundant memory cell to be disposed at thecenter while maintaining the continuity of the layout units of thedirect peripheral circuits and the general yield of the memory cells anddirect peripheral circuits to be improved. Further, it allows thedefective occurrence rate to be reduced and the quality of the redundantmemory cell to be improved as compared to the case of disposing theredundant memory cell at the peripheral part.

The effects obtained by the typical one of the inventions disclosed inthe present specification will be explained below briefly.

(1) The quality of the redundant memory cell may be improved in themanufacturing process of the semiconductor memory by disposing theredundant memory cell approximately at the center of the word line andbit line directions of the memory cell array;

(2) The production yield of the memory cells and direct peripheralcircuits may be improved because it is possible to maintain the normalrepetition of the layouts of the direct peripheral circuits such as thesub-word drivers and sense amplifiers adjacent to the memory cell evenwhen the redundant memory cell is disposed at the center; and

(3) The general yield in the layout of the highly integratedsemiconductor memory may be improved and the total chip cost may bereduced including testing time by the effects (1) and (2).

The above-mentioned and other objects and the novel characteristics ofthe invention will be apparent from the following description and theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a) and 1(b) are a layout and a partially enlarge view thereofshowing a semiconductor memory according to one embodiment of theinvention;

FIG. 2 is a circuit diagram showing a memory cell array and itsperipheral circuits in the semiconductor memory of the embodiment;

FIGS. 3(a), 3(b) and 3(C)are layouts showing the memory cell array andthe direct peripheral circuits;

FIGS. 4(a) and 4(b) are layouts showing the comparison of repeatingunits of the direct peripheral circuits;

FIG. 5 is an explanatory diagram showing a layout method of sub-worddrivers;

FIGS. 6 through 8 are a circuit diagram, a plan view and a section viewshowing the sub-word driver;

FIGS. 9(a) and 9(b) are a circuit diagram and a layout showing senseamplifiers; and

FIGS. 10(a) and 10(b) are layouts showing a memory cell array and directperipheral circuits in a semiconductor memory which is the premise ofthe present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A preferred embodiment of the invention will be explained below indetail with reference to the drawings. It is noted that the samecomponents are denoted by the same reference numerals throughout thedrawings for explaining the embodiment and a repeated explanationthereof will be omitted.

At first, the configuration of a semiconductor memory of the presentembodiment will be explained with reference to FIG. 1.

The semiconductor memory of the present embodiment is a 64 M-bit or 256M-bit DRAM using a hierarchical word line structure or a multi-divisionbit line structure. Main row decoder regions 11, main word driverregions 12, column decoder regions 13, peripheral circuit/bonding padregions 14, memory cell arrays 15, sense amplifier regions 16, sub-worddriver regions 17, intersection regions 18 and the like are formed on amemory chip 10, i.e., on one semiconductor chip, by the knownsemiconductor manufacturing technology. In FIG. 1, the horizontaldirection is the row direction (word line direction) and the verticaldirection is the column direction (bit line direction).

In the DRAM, memory regions comprising the memory cell array 15 andothers are disposed divisionally at the left and right sides in the rowdirection and at the upper and lower sides in the column direction ofthe memory chip 10 as shown in FIG. 1. The memory regions disposed onthe left and right sides are disposed in a pair interposing the main rowdecoder region 11 disposed at the center therebetween via the main worddriver regions 12 disposed corresponding to the respective memoryregions. The column decoder regions 13 disposed corresponding to therespective memory regions are disposed at the center of the upper andlower memory regions. Provided further at the center thereof as theperipheral circuit/bonding pad region 14 are a row address buffer, acolumn address buffer, a pre-decoder, a timing generating circuit and adata input/output circuit as well as a bonding pad for connecting withthe external devices.

In the memory region, the sense amplifier region 16 is disposed in thecolumn direction of the memory cell array 15 and the sub-word driverregion 17 is disposed in the row direction. An FX driver (for drivingthe sub-word driver) and a control circuit (switch MOS transistor or thelike) of the sense amplifier group are also disposed at the intersectionregion 18 of the sense amplifier region 16 and the sub-word driverregion 17 (See FIG. 2). The word line is set in the row direction andthe bit line in the column direction with respect to the memory cellarray 15. It is apparent that the invention may be applied when they aredisposed in the opposite way.

Specifically, in the semiconductor memory of the present embodiment,main word lines and pre-decoder lines (FXB lines) for controlling thesub-word drivers are outputted to the right and left from the main rowdecoder region 11 and the main word driver region 12 at the center ofthe long edge. The peripheral circuit/bonding pad region 14 is disposedat the center of the short edge and the column decoder regions 13 aredisposed between the peripheral circuit/bonding pad region 14 and thememory region. A column selection signal line YS controls a large numberof sense amplifiers in the upper or lower memory region. A redundantmemory cell is disposed approximately at the center of one memory cellarray 15. It is possible to provide the redundant memory cell in all ofthe memory cell arrays 15 or to provide every other memory cell array orevery other several memory cell arrays. The number of the redundantmemory cells is determined by a trade-off between the yield and the chiparea.

FIG. 2 is a circuit diagram simplifying the memory cell array 15 and itsperipheral circuits and shows the circuits contained in each region suchas the main row decoder region 11, the main word driver region 12, thecolumn decoder region 13, the memory cell array 15, the sense amplifierregion 16, the sub-word driver region 17, the intersection region 18 andothers as well as an input circuit 51, a pre-decoder 52, a mainamplifier 61, an output circuit 62 and others.

The memory cell array 15 comprises-a plurality of memory cells of 64K-bits in a pair of 256 sub-word lines ×256 bit lines for examplearrayed two-dimensionally. A main word line MWB (B is inversivedenotation of MW. The same applies to other signal lines) and a sub-wordline SW are disposed in the horizontal direction and bit lines BL andBLB and the column selecting signal line YS are disposed in the verticaldirection. The hierarchical word line scheme is adopted for the wordline structure and the two sub-array shared scheme is adopted for thesense amplifier. An over-drive scheme, i.e., the scheme of driving thesense amplifier driving line CSP at a voltage level of VDD at first andthen at a voltage level of VDL later, is adopted to quicken the speed.These are known technologies in IEEE Journal of Solid-State Circuit,Vol. 31, No. 9, September 1996, “A 29-ns 64-Mb DRAM with HierarchicalArray Architecture”.

The sub-word driver regions 17 are disposed adjacent to and on the rightand left of the memory cell array 15. Inputs to the sub-word driver arethe main word line MWB and the pre-decoder line FX and its output is thesub-word line SW. Sense amplifier drivers (although three NMOStransistors are shown in the figure, PMOS transistors may be used on thecharge side) and a switch transistor IOSW of local IO lines LIO and LIOBand main IO lines MIO and MIOB are provided in the intersection region18 of the sense amplifier region 16 and the sub-word driver region 17 asshown in the figure.

Further, although not shown in the figure, pre-charge circuits and FXdrivers such as sense amplifier driving lines CSP and CSN, local IOlines LIO and LIOB and main IO lines MIO and MIOB may be disposed inorder to enhance the performance further. Beside those, the inputcircuit 51, the pre-decoder 52, the main word driver, the columndecoder, the main amplifier 61 and the output circuit 62 are shown inFIG. 2. Further, in the figure, the reference symbols (SHR1 and SHR2)denote shared sense amplifier isolating signal lines, (SAP1 and SAP2)sense amplifier charging signal lines and (SAN) a sense amplifierdischarging signal line.

Further, an internal step-down scheme is used to lower power consumptionand to enhance the reliability of micro-devices and voltage VPERI (2.5V) which is lower than the power voltage VDD (3.3 V) is used for theperipheral circuits and voltage VDL (2.0 V) which is also lower than thepower voltage is used as memory cell storage voltage. It is noted thatan input/output circuit uses the voltage VDD to interface with theoutside. While it has been openly known, voltage VPP boosted by a chargepumping operation is necessary as selection voltage of the sub-word lineSW in order to write voltage VDL to the memory cell. Then, the voltageVPP is supplied as the operating voltage of the main word driver and thesub-word driver. Plate voltage VPLT and bit line pre-charge voltage VBLRsupply 1.0 V which is a half of the voltage VDL. Substrate voltage VBBis −1.0 V.

This hierarchical word line structure allows the pitch of the metallines of the main word lines (MW and MWB) and the pre-decoder lines (FXand FXB) to be relaxed more than that of the memory cell and theproduction yield of the metal lines to be enhanced by hierachizing theword lines to the main word lines and the sub-word lines SW and bysharing a set of main word lines by a plurality of sub-word lines SW.

In this hierarchical word line structure, the sub-word lines SW lined upin the row direction are outputs of the sub-word drivers and the mainword lines MW and MWB outputted from the main word driver as well as thepre-decoder lines FX and FXB outputted from the pre-decoder line FXdriver are inputted to the sub-word drivers to implement logicaloperations. A specific sub-word driver outputs High level voltage to thesub-word line SW to start reading and writing operations of all memorycells connected to the sub-word line SW when the main word lines MW andMWB, i.e., its input, and the pre-decoder lines FX and FXB in the columndirection are selected.

During the reading operations an arbitrary memory cell within the memorycell array 15 is designated by selecting the sub-word line SW by thesub-word driver and by selecting the bit lines BL and BLB by the columndecoder and data of this memory cell is amplified by the sense amplifierand is then read by the local IO lines LIO and LIOB and the main IOlines MIO and MIOB to be outputted from the output circuit 62 via themain amplifier 61. During the writing operation, an arbitrary memorycell is designated by the sub-word line SW and the bit lines BL and BLBin the same manner and data may be written from a writing circuit(provided in parallel with the main amplifier 61, not shown in FIG. 2).

FIGS. 3(a), 3(b) and 3(c) are layouts showing the basic structure of thememory cell array 15 and the direct peripheral circuits of the senseamplifier region 16 and the sub-word driver region 17 adjacent to thememory cell array 15 of the present embodiment.

As for the memory cell array 15, a word redundant memory cell isdisposed approximately at the center in the word line W direction and acolumn redundant memory cell is disposed approximately at the center inthe bit line BL direction with respect to the normal memory cell asshown in FIG. 3(a). Thereby, the quality of the redundant memory cell isimproved as compared to the case when the redundant memory cell isdisposed at the peripheral part. As the redundant memory cell isdisposed at the center, the disposition of the sub-word driver SWD inthe sub-word driver region 17 and of the sense amplifier SA in the senseamplifier region 16 are contrived specifically.

For instance, as for the sub-word driver SWD, the repeating unit isfixed even at the center part where there is the redundant memory cellas shown in FIG. 3b and the sub-word driver SWD is increased by theredundant memory cell by adding a layout having a size smaller than therepeating unit, e.g., a half, at the end of the memory cell array 15. Inthe figure, the repeating unit of the normal sub-word driver cellcombined with the redundant sub-word driver cell at the center is equalwith the neighboring repeating units. The additional cell exists for thenormal sub-word driver cell and its boundary structure is the same withthe others. End processing cells are disposed at the both ends.

As for the sense amplifier SA, the repeating unit of the normal senseamplifier cell combined with the redundant sense amplifier cell isdisposed at the center neighboring with the repeating units of only thenormal sense amplifiers as shown in FIG. 3(c) similarly to the sub-worddriver SWD and an additional cell whose size is a half of the normalsense amplifier cell is disposed at the end of the memory cell array 15.End processing cells are also disposed at the both ends. Thus, thedirect peripheral circuits (sub-word driver SWD and sense amplifier SA)connected to the redundant memory cells may be realized within the samerepetition without making a special layout.

FIGS. 4(a) and 4(b) are layouts showing the units of repetition of thedirect peripheral circuits of the sub-word driver and the senseamplifier, wherein FIG. 4b shows the repeating method according to theembodiment of the invention and FIG. 4(a) shows a comparative examplecorresponding to that.

Here, Unit 1 is a repeating unit of 16 times. Unit 2 is a layout unitsmaller than that and is used only once within the memory cell array 15.The reference symbol (N) denotes a normal memory cell related circuitand (R) a redundant memory cell related circuit. The end processingcells are necessary in either cases to add a half of contact, to feedwell and to connect wires.

It is presumed in these two layouts that the redundant memory cell isdisposed at the center of the memory cell array 15. In the comparativecase in FIG. 4(a), the Unit 1 is a layout of the normal memory cellrelated circuit. The Unit 2 is a layout of the redundant memory cellrelated circuit. It is difficult to lay out the Unit 2 so as to cut intothe repetition of the Unit 1. It is because the scale of the Unit 2 istoo small so that the efficient layout cannot be made by sharing theparts.

In contrary to that, the increase of the circuit due to the redundantmemory cell is managed by providing the Unit 2 at the end whilemaintaining the repetition of the Unit 1 including the redundant memorycell in the present embodiment as shown in FIG. 4(b). The unit 2 locatedat the end has the same shape at the boundary with the Unit 1 with theboundary of the Units 1. The half of the Unit 1 of #9 at the center isused for the redundant cell and the other half thereof is used for thenormal cell.

FIG. 5 is an embodiment in which the concept of the present invention inFIG. 3 and FIG. 4 are applied to the layout of sub-word driver.

Suppose that the memory cell array 15 has 256 normal sub-word lines and8 redundant sub-word lines. One sub-word driver implements logicalprocessing by one main word line MWB and one of eight pre-decoder linesnot shown and outputs one sub-word line. The Unit 1 of the layout unitof this sub-word driver is a circuit which inputs two of the main wordlines MWB 0 and 1, which implements logical processing with fourpre-decoder lines and which outputs four sub-word lines.

The unit 2 is a circuit which inputs one of the main word lines MWB,which implements logical processing with four pre-decoder line and whichoutputs eight sub-word lines.

However, the Unit 1 may be laid out in a width of 16 word lines and theUnit 2 in a width of 8 word lines of the memory cell. It is because thesub-word lines are disposed alternately on the memory cell array 15 fromthe two sub-word driver regions 17 adjacent to the memory cell array 15.

The redundant main word line RMWB and the normal main word line MWB 16are inputted in the Unit 1 of #9. It is merely different from the otherUnit 1 in that one normal main word line MWB among two lines is replacedwith the redundant main word line RMWB. The Unit 2 of #17 inputs thenormal main word line MWB 31 and outputs four normal sub-word lines. Thelayout structure of the boundary between the Unit 1 of #16 and the Unit2 of #17 is the same with the normal boundary layout between the Units1.

FIGS. 6 through 8 are a circuit diagram of the sub-word driver and planand section views of the layout, wherein the circuit diagram in FIG. 6shows four sub-word line segments and the section view in FIG. 8 shows asectional structural view of the part under a gate with respect to theplan view of FIG. 7.

In FIG. 7, a layout unit surrounded by a dot chain line corresponds tothe Unit 1 in FIG. 5. The reference symbols (MWBn) and (MWBn+1) denotethe main word lines and (FXBm) the pre-decoder line. Specifically, inthe present invention, the sub-word driver for the redundant memory cellmay be obtained by replacing the normal main word line MWBn or MWBn+1 bythe redundant main word line RMWB.

The sub-word driver comprises one PMOS transistor and two NMOStransistors as shown in FIG. 6 for example. When the main word line MWBis Low, the pre-decoder line FXB is Low and the pre-decoder line FX isHigh, the sub-word line SW is put into the state of selecting High level(VPP). The pre-decoder lines FXB and FX are always required to have thecomplementary potential relationship in the sub-word driver of thisscheme.

In the layout of the sub-word driver, while eight sub-word lines SW0through SW14 (even Nos.) are outputted as shown in FIG. 7, eightsub-word lines SW1 through SW15 (odd Nos.) are wired from the adjacentsub-word drivers on the right and left not shown, so that 16 sub-wordlines SW0 through SW15 in total are disposed in the longitudinaldimension in the figure.

A main word line MWB in a metal 2 layer M2 and a sub-word line SW in ametal 1 layer M1 run in the transverse direction in FIG. 7 and apre-decoder line FX of a metal 3 layer M3 and power lines (VPP and VSS)are disposed in the vertical direction. A source/drain within thesub-word driver is taken out by the metal 1 layer M1. The metal layersmay be not three but two when a bit line layer is used for connectingthe devices. The output of the sub-word line is transformed from themetal 1 layer M1 to a gate layer FG to be sent to the memory cell array15 at the both right and left ends of the sub-word driver.

Further, the sub-word driver is flown on a P-type semiconductorsubstrate P-Sub as shown in the section view of the sub-word driver inFIG. 8. FIG. 8(a) shows a DWELL isolating structure and FIG. 8(b) showsa DWELL non-isolating structure. The triple well structure of (a)requires an isolating region at the boundary of the memory cell array 15and the sub-word driver. The voltage VPP is applied to an N-well regionNW of the sub-word driver, 0 V is applied to a P-well region PW of theNMOS similarly to the P-Sub and negative voltage VBB is applied to aP-well PW of the memory cell array 15. The triple-well structure of (b)requires no isolating region because the memory cell array 15 and thesub-word driver are formed on the DW. Negative voltage VBB is applied tothe PW of the sub-word driver and the memory cell array 15.

The triple-well structure of the memory cell array 15 is widely used inDRAMs of 64 M-bits and thereafter as means for preventing noise from theperipheral circuits such as the sub-word driver and the sense amplifierto the memory cell, for enhancing the performance of the MOS transistor(a short channel MOS may be utilized because a well-bias of P well ofthe peripheral circuit is 0 V) and for strengthening the electrostaticprotection by applying 0 V to the P-Sub.

FIGS. 9(a) and 9(b) are a circuit diagram and a layout of the senseamplifier to which the concept of the invention in FIG. 3 and FIG. 4 isapplied.

A shared scheme of sharing sense amplifiers among the neighboring memorycells is adopted for this sense amplifier as shown in FIG. 9(a). Inamplifying signals, a signal of a shared line SHR on the non-selectedmemory cell on the selected memory cell is changed to the voltage VPPand a signal of a shared sense amplifier isolating signal line SHR ischanged to 0 V to isolate the bit lines BL and BLB from the senseamplifier by a cut MOS transistor. The reference symbol (PCB) denotes abit line pre-charging signal line, (VBLR) bit line pre-charging voltage,(CSP and CSN) sense amplifier driving lines, and (IO1, I02, IO1B andI02B) IO lines or actually local IO lines.

As for the layout of the sense amplifier, four sense amplifiers SA areset as a basic repeating unit (Unit 1) of the layout as shown in FIG.9(b). It includes two column selecting signal lines YS, one power lineor signal line PS and three signal lines of the metal 3 layer M3.Although the column selecting signal line YS is used in the senseamplifier SA, the power line or the signal line PS merely passes abovethe sense amplifier. One column selecting signal line YS controls twosense amplifiers SA. The three lines of the metal 3 layer M3 aredisposed within the width of the four sense amplifiers SA. Accordingly,it is appropriate to set the four sense amplifiers SA as one layoutunit.

When there are two sense amplifiers SA for the redundant memory cell atthe center, one column selecting signal line YS is replaced with aredundant column selecting signal line RYS while maintaining the samerepetition by combining two sense amplifiers SA for the redundant memorycell and two normal sense amplifiers SA as shown in the figure. When thehatched part is to be specially laid out, the mutual relationship amongthe metal 3 layers M3 collapses and the space of the metal 3 layer M3becomes insufficient. Then, the layout (Unit 2) of the sense amplifierSA of a half width is added at the end for the increase of the redundantsense amplifier SA. It is not difficult to add it because it is added atthe end.

Therefore, since the semiconductor memory of the present embodimentallows the redundant memory cell to be disposed almost at the center ofthe memory cell array 15 and the direct peripheral circuits such as thesub-word driver and the sense amplifier adjacent to the memory cellarray 15 to be disposed while maintaining the normal repeating unit, itallows the quality of the redundant memory cell to be improved and theproduction yield of the memory cell array 15 and the direct peripheralcircuits to be improved.

Although the invention devised by the inventor has been explained inconcrete based on the embodiments thereof, the invention is not limitedto the embodiments described above and may be modified variously withinthe scope of the gist.

As described above, the inventive semiconductor memory is useful to ahighly integrated semiconductor memory and to a semiconductor memory of64 M-bits or 256 M-bits DRAM or synchronous DRAM in which the inventionis effectively applied to the disposition of the redundant memory celland the layout of the word driver and the sense amplifier connected tothe redundant memory cell. Still more, it is widely applicable to otherhighly integrated DRAMs and other semiconductor memories such as SRAM,RAM, ROM, PROM, EPROM and EEPROM.

What is claimed is:
 1. A semiconductor memory comprising: a plurality ofmemory cells which are disposed two-dimensionally in the word line andbit line directions in a memory cell array, said plurality of memorycells are composed of a large number of normal memory cells and a smallnumber of redundant memory cells; and peripheral circuits having worddrivers and sense amplifiers on the outside of said memory cell arraywhich are capable of switching an operation to said redundant memorycell when said normal memory cell is defective, wherein said redundantmemory cells are disposed approximately at the center in said word lineand bit line directions, a layout unit of said word drivers and senseamplifiers connected to said redundant memory cell is substantiallyequal to what layouts for the redundant memory cell and for the normalmemory cell are combined and is substantially equal to the layout unitof said normal memory cell and a control input of said word driver orsaid sense amplifier is replaced among those for the normal andredundant ones.
 2. The semiconductor memory according to claim 1,wherein said word driver is a sub-word driver in the hierarchical wordline scheme, one layout unit inputs a plurality of main word lines and alayout unit containing the sub-word driver connected to said redundantmemory cell is different from a layout unit for said normal memory cellonly in that one main word line is replaced with a redundant main wordline signal.
 3. The semiconductor memory according to claim 1, whereinsaid sense amplifier has one layout unit by containing a plurality ofsense amplifiers, a plurality of column selecting signal lines forcontrolling them, other control lines and power lines and the layoutunit of sense amplifier connected to said redundant memory cell isdifferent from the layout unit for said normal memory cell only in thatone column selecting signal line is replaced with a redundant columnselecting signal line.
 4. The semiconductor memory according to claims1, 2 or 3, wherein said semiconductor memory is a highly integratedDRAM.